Tuesday, August 07, 2012

Latchup and its remedies:

What is Latchup?

Latch-up is a condition in which the parasitic components give rise to the Establishment of low
 resistance conducting path between VDD and VSS with Disastrous results. 

(in the figure, moat = substrate)

The start of trouble!

Electron flow builds up voltage

The forward biased source injects some holes

The holes are swept into the substrate

Voltage drop at the n-channel source end.

The electrons are swept into the moat

More current means a bigger voltage and more holes injected.

Latch Up!


How to avoid Latchup? 

Latch up effect can be minimized by 

 1.   Putting the isolation between pmos and nmos regions. 

 2. Changing the dopping concentrations thus reducing the gain of pnpn device. SOI (silicon on insulator)doesnt have any latch up problem. because of latch up effect there is the short between power lines and the continuous current flows through the device till the power down. This results into malfunctioning of the device, resulting into its damage. This latch problem is observed in case of two transistors arranged side by side forming pnpn/npnp structure.

Hardwork Can Never Ever Fails...
Best Luck...

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