Wednesday, August 08, 2012

Memory Hirerarchy in Embedded Systems

Memory Hierarchy

The cache memory is defined as the first level of memory after the Registers. In the memory hierarchy, it is placed right below the processor registers as shown in the figure above.

Speed Vs Distance Vs Size of the Memory
 The above diagram shows the position of the Cache memory based on the Speed, Distance from the Processor and the Size.

How the Processor check for the data?

The cache is generally made up of SRAM because of the high speed of operation of SRAMs and the faster a cache operates, faster data can be made available to the processor for processing.

Components in the Memory Hierarchy

The cache stores in it the data of memory locations that the processor uses repeatably or is expected to use very soon in future. When the processor wants to access data of a certain memory location, the data might be present in cache or not, this is defined by the terms cache hit and cache miss respectively.

Cache Miss

Cache Miss

When the processor does not find, the memory location which it wants to access, stored in the cache it has to fetch the data from the main memory. As the data is missing in the cache this is termed as a cache miss.

Cache Hit

Cache Hit
If the memory location is present in the cache, processor can fetch the data from cache itself and need not go to the main memory to fetch it. This is termed as a cache hit.

Temporal Locality

Temporal Locality
A memory location accessed once will be accessed again soon and hence need to be stored close to the processor. This is an assumption and if the same data is required in the near future, we can save time by doing this.

Spatial Locality

Spatial Locality

The memory locations around the memory that the processor accesses might also be accessed by the processor soon and hence need to stored close the processor in the cache.This is also based on an assumption and we believe that the data next to the current location will be required for the next computation.

I think this below 3 Dimensional Diagram will make the Memory Hierarchy much more clear to the readers.

How the CPU Access the Memory

  1. The address of the needed data is formed in the processor execution or instruction-fetch unit. Most addresses are then mapped from virtual to real through the Translation Look aside Buffer (TLB). Certain ranges of addresses are not mapped, and bypass the TLB.
  2. Most addresses are presented to the primary cache, a cache in the processor chip. If a copy of the data with that address is found, it is returned immediately. Certain address ranges are never cached; these addresses pass directly to the bus.
  3. When the primary cache does not contain the data, the address is presented to the secondary cache. If it contains a copy of the data, the data is returned immediately. The size and the architecture of the secondary cache differ from one CPU model to another.
  4. The address is placed on the system bus. The memory module that recognizes the address places the data on the bus.



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