Thursday, August 02, 2012
Two bipolar transistors (T3 and T4), one nMOS and one pMOS transistor (both enhancement-type devices, OFF at Vin=0V)
--T2 ON - supplies current to base of T4
--T4 base voltage set to Vdd.
--T4 conducts & acts as current source to charge load CL towards Vdd.
--Vout rises to Vdd - Vbe (of T4)
Note : Vbe (of T4) is base-emitter voltage of T4.
(pullup bipolar transistor turns off as the output approaches
5V - Vbe (of T4))
Output logic levels will be good & will be
close to rail voltages since VCEsat is
Inverter has high input
impedance, i.e., MOS gate input
Inverter has low output impedance
Inverter has high drive capability but
occupies a relatively small area
However, this is not a good arrangement to
implement since no discharge path
Hardwork Can Never Ever Fails..