Thursday, August 02, 2012

BI-CMOS Inverter-working


Two bipolar transistors (T3 and T4), one nMOS and one pMOS transistor (both enhancement-type devices, OFF at Vin=0V)
The MOS switches perform the logic function & bipolar transistors drive output loads

Vin = 0 

--T1 is off.   Therefore T3 is non-conducting
--T2 ON - supplies current to base of T4
--T4 base voltage set to Vdd.
--T4 conducts & acts as current source to charge load CL towards Vdd.
--Vout rises to Vdd - Vbe (of T4) 
  Note :          Vbe (of T4) is base-emitter voltage of  T4.
 (pullup bipolar transistor turns off as the output approaches
 5V - Vbe (of T4))
  Vin = Vdd 

--T2 is off. Therefore T4 is non-conducting.
--T1 is on and supplies current to the base of T3
--T3 conducts & acts as a current sink to discharge load CL towards 0V.
--Vout falls to 0V+ VCEsat (of T3) 
Note : VCEsat (of T3) is saturation V from T3 collector to emitter 

T3 & T4 present low impedances when turned on into saturation & load CL will be
  charged or discharged rapidly
          Output logic levels will be good & will be close to rail voltages since VCEsat  is quite
   small & VBE » 0.7V. Therefore, inverter has high noise margins 
          Inverter has high input impedance, i.e., MOS gate input
          Inverter has low output impedance
          Inverter has high drive capability but occupies a relatively small area
          However, this is not a good arrangement to implement since no discharge path
   exists for current from the base of either bipolar transistor when it is being turned
   off, i.e.,  
                     when Vin=Vdd, T2 is off and no
                conducting path to the base of T4 exists  
                    when Vin=0,      T1 is off and
                                         no conducting path to the base of T3 exists
   This will slow down the action of the circuit

Hardwork Can Never Ever Fails..
Best Luck...


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